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data sheet, feb. 2003 microcontrollers never stop thinking. c515c 8-bit single-chip microcontroller
edition 2003-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, feb. 2003 c515c 8-bit single-chip microcontroller microcontrollers never stop thinking.
enhanced hooks technology? is a trademark of infineon technologies. c515c data sheet revision history: 2003-02 previous version: 2000-08 page subjects (major changes since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 2003-02 c515c 8-bit single-chip microcontroller features full upward compatibility with sab 80c515a on-chip program memory (with optional memory protection) ? c515c-8r 64 kbytes on-chip rom ? c515c-8e 64 kbytes on-chip otp ? alternatively up to 64 kbytes external program memory 256 bytes on-chip ram 2 kbytes of on-chip xram up to 64 kbytes external data memory superset of the 8051 architecture with 8 datapointers up to 10 mhz external operating frequency (1 s instruction cycle time at 6 mhz external clock) on-chip emulation support logic (enhanced hooks technology) current optimized oscillator circuit and emi optimized design (further features are on next page) figure 1 c515c functional units mca03646 on-chip emulation support module port 0 port 1 port 2 port 3 ram 256 x 8 xram cpu t0 t1 usart i/o i/o i/o i/o 8 datapointer port 7 port 6 port 5 port 4 capture/compare unit timer 2 full-can controller 10 bit adc (8 inputs) oscillator watchdog save modes idle/ power down slow down ssc (spi) interface i/o i/o i/o analog/ digital input power bit 8 2k x 8 c515c-8r : 64k x 8 rom program memory c515c-8e : 64k x 8 otp
c515c data sheet 2 2003-02 eight ports: 48 + 1 digital i/o lines, 8 analog inputs ? quasi-bidirectional port structure (8051 compatible) ? port 5 selectable for bidirectional port structure (cmos voltage levels) full-can controller on-chip ? 256 register/data bytes are located in external data memory area ? max. 1 mbaud at 8 - 10 mhz operating frequency three 16-bit timer/counters ? timer 2 can be used for compare/capture functions 10-bit a/d converter with multiplexed inputs and built-in self calibration full duplex serial interface with programmable baudrate generator (usart) ssc synchronous serial interface (spi compatible) ? master and slave capable ? programmable clock polarity/clock-edge to data phase relation ? lsb/msb first selectable ? 2.5 mhz transfer rate at 10 mhz operating frequency seventeen interrupt vectors, at four priority levels selectable extended watchdog facilities ? 15-bit programmable watchdog timer ? oscillator watchdog power saving modes ?slow-down mode ? idle mode (can be combined with slow-down mode) ? software power-down mode with wake-up capability through int0 or rxdc pin ? hardware power-down mode cpu running condition output pin ale can be switched off multiple separate v dd / v ss pin pairs p-mqfp-80-1 package temperature ranges: sab-c515c versions: t a = 0 to 70 c saf-c515c versions: t a = -40 to 85 c sah-c515c versions: t a = -40 to 110 c note: versions for extended temperature range -40 c to 110 c (sah-c515c) are available on request. the c515c is an enhanced, upgraded version of the sab 80c515a 8-bit microcontroller which additionally provides a full can interface, a spi compatible synchronous serial interface, extended power save provisions, additional on-chip ram, 64k of on-chip program memory, two new external interrupts and rfi related improvements. with a maximum external clock rate of 10 mhz it achieves a 600 ns instruction cycle time (1 s at 6 mhz).
c515c data sheet 3 2003-02 the c515c-8r contains a non-volatile 64 kbytes read-only program memory. the c515c-l is identical to the c515c-8r, except that it lacks the on-chip program memory. the c515c-8e is the otp version in the c515c microcontroller with an on-chip 64 kbytes one-time programmable (otp) program memory. the c515c is mounted in a p-mqfp-80-1 package. if compared to the c515c-8r and c515c-l, the c515c-8e otp version additionally provides two features: the wake-up from software power down mode can, additionally to the external pin p3.2/int0 wake-up capability, also be triggered alternatively by a second pin p4.7/rxdc. for power consumption reasons the on-chip can controller can be switched off. note: the term c515c refers to all versions described within this document unless otherwise noted. ordering information the ordering code for infineon technologies? microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set the specified temperature rage the package and the type of delivery for the available ordering codes for the c515c please refer to the ? product information microcontrollers ?, which summarizes all available microcontroller variants. note: the ordering codes for the mask-rom versions are defined for each product after verification of the respective rom code. table 1 differences in internal program memory of the c505 mcus device internal program memory rom otp c515c-lm ?? c515c-8rm 64 kbytes ? c515c-8em ? 64 kbytes
c515c data sheet 4 2003-02 figure 2 logic symbol mcl02714 xtal1 xtal2 reset ea ale psen hwpd c515c port 0 8 bit digital i/o port 1 port 2 port 3 v aref agnd v digital inputs port 7 port 6 port 5 port 4 pe/swd 8 bit digital i/o 8 bit digital i/o 8 bit digital i/o 8 bit digital i/o 8 bit digital i/o 1 bit digital i/o 8 bit analog/ v ssclk ddclk v ssext v ddext v cpur sse1 v v dde1 v sse2 v dde2 dd1 v ss1 v
c515c data sheet 5 2003-02 figure 3 c515c pin configuration p-mqfp-80-1 (top view) mcp02715 12 n.c. 345 p6.7/ain7 6 p6.6/ain6 7 p6.5/ain5 8 p6.4/ain4 9 p6.3/ain3 10 p6.2/ain2 11 p6.1/ain1 12 p6.0/ain0 13 14 15 p3.0/rxd 16 p3.1/txd 17 p3.2/int0 18 p3.3/int1 19 p3.4/t0 20 p3.5/t1 v agnd 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ea ale psen cpur p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p4.7/rxdc p4.6/txdc p4.5/int8 p4.4/sls p4.3/sto pe/swd p4.2/sri p4.1/sclk p4.0/adst n.c. hwpd p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 v sse1 p3.6/wr p3.7/rd p1.7/t2 p1.6/clkout p1.5/t2ex p1.4/int2 p1.3/int6/cc3 p1.2/int5/cc2 p1.1/int4/cc1 p1.0/int3/cc0 xtal2 xtal1 p2.0/a8 p2.1/a9 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 61 p5.6 p5.7 ss1 v v dde1 dd1 v p2.2/a10 aref v reset c515c v ssclk ddclk v p7.0/int7 v ddext ssext v v dde2 sse2 v
c515c data sheet 6 2003-02 table 2 pin definitions and functions symbol pin number i/o 1) function p-mqfp-80-1 reset 1i reset a low level on this pin for the duration of two machine cycles while the oscillator is running resets the c515c. a small internal pullup resistor permits power-on reset using only a capacitor connected to v ss . v aref 3? reference voltage for the a/d converter v agnd 4? reference ground for the a/d converter p6.0-p6.7 12-5 i port 6 is an 8-bit unidirectional input port to the a/d converter. port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs. p7.0 / int7 23 i/o port 7 is an 1-bit quasi-bidirectional i/o port with internal pull-up resistor. when a 1 is written to p7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. as input, p7.0 being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistor. if p7.0 is used as interrupt input, its output latch must be programmed to a one (1). the secondary function is assigned to the port 7 pin as follows: p7.0 int7 , interrupt 7 input
c515c data sheet 7 2003-02 p3.0-p3.7 15-22 15 16 17 18 19 20 21 22 i/o port 3 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: p3.0 rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 int0 external interrupt 0 input / timer 0 gate control input p3.3 int1 external interrupt 1 input / timer 1 gate control input p3.4 t0 timer 0 counter input p3.5 t1 timer 1 counter input p3.6 wr wr control output; latches the data byte from port 0 into the external data memory p3.7 rd rd control output; enables the external data memory table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 8 2003-02 p1.0 - p1.7 31-24 31 30 29 28 27 26 25 24 i/o port 1 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. the port is used for the low-order address byte during program verification. port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). the secondary functions are assigned to the port 1 pins as follows: p1.0 int3 cc0 interrupt 3 input / compare 0 output / capture 0 input p1.1 int4 cc1 interrupt 4 input / compare 1 output / capture 1 input p1.2 int5 cc2 interrupt 5 input / compare 2 output / capture 2 input p1.3 int6 cc3 interrupt 6 input / compare 3 output / capture 3 input p1.4 int2 interrupt 2 input p1.5 t2ex timer 2 external reload / trigger input p1.6 clkout system clock output p1.7 t2 counter 2 input xtal2 36 i xtal2 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal2 should be driven, while xtal1 is left unconnected. minimum and maximum high and low times as well as rise/fall times specified in the ac characteristics must be observed. table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 9 2003-02 xtal1 37 o xtal1 output of the inverting oscillator amplifier. p2.0-p2.7 38-45 i/o port 2 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup resistors when issuing 1's. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register. cpur 46 o cpu running condition this output pin is at low level when the cpu is running and program fetches or data accesses in the external data memory area are executed. in idle mode, hardware and software power down mode, and with an active reset signal cpur is set to high level. cpur can be typically used for switching external memory devices into power saving modes. psen 47 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods, except during external data memory accesses. the signal remains high during internal program execution. table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 10 2003-02 ale 48 o the address latch enable output is used for latching the address into external memory during normal operation. it is activated every six oscillator periods, except during an external data memory access. ale can be switched off when the program is executed internally. ea 49 i external access enable when held high, the c515c executes instructions always from the internal rom. when held low, the c515c fetches all instructions from external program memory. note: for the rom protection version ea pin is latched during reset. p0.0-p0.7 52-59 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullup resistors when issuing 1's. port 0 also outputs the code bytes during program verification in the c515c. external pullup resistors are required during program verification. p5.0-p5.7 67-60 i/o port 5 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 5 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 5 can also be switched into a bidirectional mode, in which cmos levels are provided. in this bidirectional mode, each port 5 pin can be programmed individually as input or output. table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 11 2003-02 hwpd 69 i hardware power down a low level on this pin for the duration of one machine cycle while the oscillator is running resets the c515c. a low level for a longer period will force the part to power down mode with the pins floating. p4.0-p4.7 72-74, 76-80 72 73 74 76 77 78 79 80 i/o port 4 is an 8-bit quasi-bidirectional i/o port with internal pull-up resistors. port 4 pins that have 1?s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. p4 also contains the external a/d converter control pin, the ssc pins, the can controller input/output lines, and the external interrupt 8 input. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the alternate functions are assigned to port 4 as follows: p4.0 adst external a/d converter start pin p4.1 sclk ssc master clock output / ssc slave clock input p4.2 sri ssc receive input p4.3 sto ssc transmit output p4.4 sls slave select input p4.5 int8 external interrupt 8 input p4.6 txdc transmitter output of the can controller p4.7 rxdc receiver input of the can controller table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 12 2003-02 pe /swd 75 i power saving mode enable / start watchdog timer a low level on this pin allows the software to enter the power down, idle and slow down mode. in case the low level is also seen during reset, the watchdog timer function is off on default. use of the software controlled power saving modes is blocked, when this pin is held on high level. a high level during reset performs an automatic start of the watchdog timer immediately after reset. when left unconnected this pin is pulled high by a weak internal pull-up resistor. v ssclk 13 ? ground (0 v) for on-chip oscillator this pin is used for ground connection of the on-chip oscillator circuit. v ddclk 14 ? supply voltage for on-chip oscillator this pin is used for power supply of the on-chip oscillator circuit. v dde1 v dde2 32 68 ? supply voltage for i/o ports these pins are used for power supply of the i/o ports during normal, idle, and power down mode. v sse1 v sse2 35 70 ? ground (0 v) for i/o ports these pins are used for ground connections of the i/o ports during normal, idle, and power down mode. v dd1 33 ? supply voltage for internal logic this pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode. v ss1 34 ? ground (0 v) for internal logic this pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode. table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 13 2003-02 v ddext 50 ? supply voltage for external access pins this pin is used for power supply of the i/o ports and control signals which are used during external accesses (for port 0, port 2, ale, psen , p3.6/wr , and p3.7/rd ). v ssext 51 ? ground (0 v) for external access pins this pin is used for the ground connection of the i/o ports and control signals which are used during external accesses (for port 0, port 2, ale, psen , p3.6/wr , and p3.7/rd ). n.c. 2, 71 ? not connected these pins should not be connected. 1) i = input; o = output table 2 pin definitions and functions (cont?d) symbol pin number i/o 1) function p-mqfp-80-1
c515c data sheet 14 2003-02 figure 4 block diagram of the c515c mcb03647 oscillator watchdog osc & timing cpu timer 1 timer 2 a/d converter timer 0 s & h mux xram 2k x 8 256 x 8 ram rom/otp port 0 port 1 port 2 port 3 port 0 port 1 port 2 xtal2 xtal1 reset ale ea v agnd aref v support emulation logic 8 datapointers programmable watchdog timer psen pe/swd hwpd capture compare unit port 7 port 6 port 5 port 4 v c515c 8 bit digital i/o 8 bit analog/ multiple lines / dd ss v 64k x 8 cpur 8 bit digital i/o 8 bit digital i/o baud rate generator ssc (spi) interface digital inputs port 5 port 4 port 3 port 6 port 7 1 bit digital i/o reg./data 256 byte full-can controller interrupt unit 10 bit usart 8 bit digital i/o 8 bit digital i/o 8 bit digital i/o
c515c data sheet 15 2003-02 cpu the c515c is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 6 mhz crystal, 58% of the instructions are executed in 1 s (10 mhz: 600 ns). psw special function register (d0 h ) reset value: 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag pparity flag set/cleared by hardware after each instruction to indicate an odd/even number of ?one? bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
c515c data sheet 16 2003-02 memory organization the c515c cpu manipulates data and operands in the following five address spaces: up to 64 kbytes of internal/external program memory up to 64 kbytes of external data memory 256 bytes of internal data memory 256 bytes can controller registers / data memory 2 kbytes of internal xram data memory a 128 byte special function register area figure 5 illustrates the memory address spaces of the c515c. figure 5 c515c memory map mcd02717 00 h h 7f 0000 h external ffff h "code space" "data space" "internal data space" h 0000 h ffff external f800 h internal xram ram internal internal ram ff h h 80 function special register direct address 80 h h ff address indirect (2 kbyte) (ea = 0) (ea = 1) internal h f6ff data external memory (256 byte) controller int. can h f700 f7ff h alternatively
c515c data sheet 17 2003-02 control of xram/can controller access the xram in the c515c is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. because the xram and the can controller is used in the same way as external data memory the same instruction types (movx) must be used for accessing the xram. two bits in sfr syscon, xmap0 and xmap1, control the accesses to the xram and the can controller. syscon special function register (b1 h ) c515c-8r reset value: x010xx01 b c515c-8e reset value: x010x001 b bit xmap0 is hardware protected. if it is reset once (xram/can controller access enabled) it cannot be set by software. only a reset operation will set the xmap0 bit again. bit function xmap1 xram/can controller visible access control control bit for rd /wr signals during xram/can controller accesses. if addresses are outside the xram/can controller address range or if xram is disabled, this bit has no effect. xmap1 = 0: the signals rd and wr are not activated during accesses to the xram/can controller xmap1 = 1: ports 0, 2 and the signals rd and wr are activated during accesses to xram/can controller. in this mode, address and data information during xram/can controller accesses are visible externally. xmap0 global xram/can controller access enable/disable control xmap0 = 0: the access to xram and can controller is enabled. xmap0 = 1: the access to xram and can controller is disabled (default after reset). all movx accesses are performed via the external bus. further, this bit is hardware protected. 76543210 bit no. msb lsb eale rmap ? b1 h syscon cswo xmap1 ?pmod xmap0 the function of the shaded bits is not described in this section.
c515c data sheet 18 2003-02 the xram/can controller can be accessed by read/write instructions (movx a,dptr, movx @dptr,a), which use the 16-bit dptr for indirect addressing. for accessing the xram or can controller, the effective address stored in dptr must be in the range of f700 h to ffff h . the xram can be also accessed by read/write instructions (movx a,@ri, movx @ri,a), which use only an 8-bit address (indir ect addressing with registers r0 or r1). therefore, a special page register xpage which provides the upper address information (a8-a15) during 8-bit xram accesses. the behaviour of port 0 and p2 during a movx access depends on the control bits xmap0 and xmap1 in register syscon and on the state of pin ea . table 3 lists the various operating conditions.
c515c data sheet 19 2003-02 modes compatible to 8051/c501 family table 3 behaviour of p0/p2 and rd /wr during movx accesses xmap1, xmap0 00 10 x1 ea = 0 movx @dptr dptr < xram/can address range a) p0/p2 bus b) rd /wr active c) ext.memory is used a) p0/p2 bus b) rd /wr active c) ext.memory is used a) p0/p2 bus b) rd /wr active c) ext.memory is used dptr xramcan address range a) p0/p2 bus (rd /wr -data) b) rd /wr inactive c) xram is used a) p0/p2 bus (rd /wr -data) b) rd /wr active c) xram is used a) p0/p2 bus b) rd /wr active c) ext.memory is used movx @ ri xpage < xramcan addr. page range a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used xpage xramcan addr. page range a) p0 bus (rd /wr -data) p2 i/o b) rd /wr inactive c) xram is used a) p0 bus (rd /wr -data only) p2 i/o b) rd /wr active c) xram is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used ea = 1 movx @dptr dptr < xram/can address range a) p0/p2 bus b) rd /wr active c) ext.memory is used a) p0/p2 bus b) rd /wr active c) ext.memory is used a) p0/p2 bus b) rd /wr active c) ext.memory is used dptr xramcan address range a) p0/p2 /0 b) rd /wr inactive c) xram is used a) p0/p2 bus (rd /wr -data) b) rd /wr active c) xram is used a) p0/p2 bus b) rd /wr active c) ext.memory is used movx @ ri xpage < xramcan addr. page range a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used xpage xramcan addr. page range a) p2 i/o p0/p2 i/o b) rd /wr inactive c) xram is used a) p0 bus (rd /wr -data) p2 i/o b) rd /wr active c) xram is used a) p0 bus p2 i/o b) rd /wr active c) ext.memory is used
c515c data sheet 20 2003-02 reset and system clock the reset input is an active low input at pin reset . since the reset is synchronized internally, the reset pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. a pullup resistor is internally connected to v dd to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v dd is applied by connecting the reset pin to v ss via a capacitor. figure 6 shows the possible reset circuitries. figure 6 reset circuitries figure 7 shows the recommended oscillator circiutries for crystal and external clock operation. mcs02721 reset c515c b) a) c) + + & reset reset c515c c515c
c515c data sheet 21 2003-02 figure 7 recommended oscillator circuitries multiple datapointers as a functional enhancement to the standard 8051 architecture, the c515c contains eight 16-bit datapointers instead of only one datapointer. the instruction set uses just one of these datapointers at a time. the selection of the actual datapointer is done in the special function register dpsel. figure 8 illustrates the datapointer addressing mechanism. figure 8 external data memory addressing using multiple datapointers mct02765 xtal1 xtal2 xtal2 xtal1 crystal/resonator oscillator mode driving from external source external oscillator signal n.c. 2 - 10 mhz c c c = 20 pf 10 pf (incl. stray capacitance) crystal mode : : resonator mode = depends on selected ceramic resonator c dph(83 ) dpl(82 ) dptr0 dptr7 .0 .1 .2 - - - - - dpsel(92 ) dpsel selected data- pointer .2 .1 .0 dptr 0 0 0 0 0 0 1 dptr 1 0 1 0 dptr 2 0 1 1 dptr 3 1 0 0 dptr 4 1 0 1 dptr 5 1 1 0 dptr 6 1 1 1 dptr 7 mcd00779 external data memory h hh
c515c data sheet 22 2003-02 enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip rom based programs is possible, too. each production chip has built-in logic for the support of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology, which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500 microcontrollers. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 9 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. mcs03280 syscon pcon tcon reset ea psen ale 0 2 port port i/o ports optional port 3 port 1 c500 mcu interface circuit enhanced hooks rport 0 rport 2 rtcon rpcon rsyscon tea tale tpsen eh-ic target system interface ice-system interface to emulation hardware
c515c data sheet 23 2003-02 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the special function register area consists of two portions: the standard special function register area and the mapped special function register area. two special function regi sters of the c515c (pcon1 and dir5) are located in the mapped special function register area. for accessing the mapped special function register area, bit rmap in special function register syscon must be set. all other special function registers are located in the standard special function register area which is accessed when rmap is cleared (?0?). as long as bit rmap is set, mapped special function register area can be accessed. this bit is not cleared by hardware automatically. thus, when non-mapped/mapped registers are to be accessed, the bit rmap must be cleared/set by software, respectively each. syscon special function register (b1 h ) c515c-8r reset value: x010xx01 b c515c-8e reset value: x010x001 b the 59 special function registers (sfrs) in the standard and mapped sfr area include pointers and registers that provide an inte rface between the cpu and the other on-chip peripherals. the sfrs of the c515c are listed in table 4 and table 5 . in table 4 they are organized in groups which refer to the functional blocks of the c515c. the can- sfrs are also included in table 4 . table 5 illustrates the contents of the sfrs in numeric order of their addresses. table 6 list the can-sfrs in numeric order of their addresses. bit function rmap special function register map bit rmap = 0: the access to the non-mapped (standard) special function register area is enabled (reset value). rmap = 1: the access to the mapped special function register area is enabled. 76543210 bit no. msb lsb eale rmap ? b1 h syscon cswo xmap1 ?pmod xmap0 the function of the shaded bits is not described in this section.
c515c data sheet 24 2003-02 table 4 special function registers - functional block block symbol name addr contents after reset cpu acc b dph dpl dpsel psw sp syscon 1) accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer system control register c515c-8r c515c-8e e0 h 2) f0 h 2) 83 h 82 h 92 h d0 h 2) 81 h b1 h b1 h 00 h 00 h 00 h 00 h xxxxx000 b 3) 00 h 07 h x010xx01 b 3) x010x001 b 3) a/d- converter adcon0 1) adcon1 addath addatl a/d converter control register 0 a/d converter control register 1 a/d converter data register high byte a/d converter data register low byte d8 h 2) dc h d9 h da h 00 h 0xxxx000 b 3) 00 h 00xxxxxx b 3) interrupt system ien0 1) ien1 1) ien2 ip0 1) ip1 tcon 1) t2con 1) scon 1) ircon interrupt enable register 0 interrupt enable register 1 interrupt enable register 2 interrupt priority register 0 interrupt priority register 1 timer control register timer 2 control register serial channel control register interrupt request control register a8 h 2) b8 h 2) 9a h a9 h b9 h 88 h 2) c8 h 2) 98 h 2) c0 h 2) 00 h 00 h xx00x00x b 3) 00 h 0x000000 b 3) 00 h 00 h 00 h 00 h xram xpage syscon 1) page address register for extended on-chip xram and can controller system control register c515c-8r c515c-8e 91 h b1 h b1 h 00 h x010xx01 b 3) x010x001 b 3) ports p0 p1 p2 p3 p4 p5 dir5 p6 p7 syscon 1) port 0 port 1 port 2 port 3 port 4 port 5 port 5 direction register port 6, analog/digital input port 7 system control register c515c-8r c515c-8e 80 h 2) 90 h 2) a0 h 2) b0 h 2) e8 h 2) f8 h 2) f8 h 2)4) db h fa h b1 h ff h ff h ff h ff h ff h ff h ff h ? xxxxxxx1 b 3) x010xx01 b 3) x010x001 b 3) watchdog wdtrel ien0 1) ien1 1) ip0 1) watchdog timer reload register interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 86 h a8 h 2) b8 h 2) a9 h 00 h 00 h 00 h 00 h
c515c data sheet 25 2003-02 serial channel adcon0 1) pcon 1) sbuf scon srell srelh a/d converter control register 0 power control register serial channel buffer register serial channel control register serial channel reload register, low byte serial channel reload register, high byte d8 h 2) 87 h 99 h 98 h 2) aa h ba h 00 h 00 h xx h 3) 00 h d9 h xxxxxx11 b 3) can controller cr sr ir btr0 btr1 gms0 gms1 ugml0 ugml1 lgml0 lgml1 umlm0 umlm1 lmlm0 lmlm1 mcr0 mcr1 uar0 uar1 lar0 lar1 mcfg db0n db1n db2n db3n db4n db5n db6n db7n control register status register interrupt register bit timing register low bit timing register high global mask short register low global mask short register high upper global mask long register low upper global mask long register high lower global mask long register low lower global mask long register high upper mask of last message register low upper mask of last message register high lower mask of last message register low lower mask of last message register high message object registers: message control register low message control register high upper arbitration register low upper arbitration register high lower arbitration register low lower arbitration register high message configuration register message data byte 0 message data byte 1 message data byte 2 message data byte 3 message data byte 4 message data byte 5 message data byte 6 message data byte 7 f700 h f701 h f702 h f704 h f705 h f706 h f707 h f708 h f709 h f70a h f70b h f70c h f70d h f70e h f70f h f7n0 h 5) f7n1 h 5) f7n2 h 5) f7n3 h 5) f7n4 h 5) f7n5 h 5) f7n6 h 5) f7n7 h 5) f7n8 h 5) f7n9 h 5) f7na h 5) f7nb h 5) f7nc h 5) f7nd h 5) f7ne h 5) 101 h xx h 6) xx h 6) uu h 6) 0uuuuuuu b 6) uu h 6) uuu11111 b 6) uu h 6) uu h 6) uu h 6) uuuuu000 b 6) uu h 6) uu h 6) uu h 6) uuuuu000 b 6) uu h 6) uu h 6) uu h 6) uu h 6) uu h 6) uuuuu000 b 6) uuuuuu00 b 6) xx h 6) xx h 6) xx h 6) xx h 6) xx h 6) xx h 6) xx h 6) xx h 6) table 4 special function registers - functional block (cont?d) block symbol name addr contents after reset
c515c data sheet 26 2003-02 ssc interface ssccon stb srb scf scien sscmod ssc control register ssc transmit buffer ssc receive register ssc flag register ssc interrupt enable register ssc mode test register 93 h 2) 94 h 95 h ab h 2) ac h 96 h 07 h xx h 3) xx h 3) xxxxxx00 b 3) xxxxxx00 b 3) 00 h timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 2) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h compare/ capture unit/ timer 2 ccen cch1 cch2 cch3 ccl1 ccl2 ccl3 crch crcl th2 tl2 t2con comp./capture enable reg. comp./capture reg. 1, high byte comp./capture reg. 2, high byte comp./capture reg. 3, high byte comp./capture reg. 1, low byte comp./capture reg. 2, low byte comp./capture reg. 3, low byte com./rel./capt. reg. high byte com./rel./capt. reg. low byte timer 2, high byte timer 2, low byte timer 2 control register c1 h c3 h c5 h c7 h c2 h c4 h c6 h cb h ca h cd h cc h c8 h 2) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h power save modes pcon 1) pcon1 power control register power control register 1 c515c-8r c515c-8e 87 h 88 h 7) 88 h 7) 00 h 0xxxxxxx b 3) 0xx0xxxx b 3) 1) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 2) bit-addressable special function registers 3) ?x? means that the value is undefined and the location is reserved. 4) this sfr is a mapped sfr. for accessing this sfr, bit pdir in sfr ip1 must be set. 5) the notation ?n? in the message object address definition defines the number of the related message object. 6) ?x? means that the value is undefined and the location is reserved. ?u? means that the value is unchanged by a reset operation. ?u? values are undefined (as ?x?) after a power-on reset operation. 7) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 4 special function registers - functional block (cont?d) block symbol name addr contents after reset
c515c data sheet 27 2003-02 table 5 contents of the sfrs, sfrs in numeric order of their addresses addr. register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 3) pcon1 4) 0xxx- xxxx b ewpd ? ? ? ? ? ? ? 88 h 3) pcon1 5) 0xx0- xxxx b ewpd ? ? ws ? ? ? ? 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex int2 int6 int5 int4 int3 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 92 h dpsel xxxx- x000 b ? ? ???.2.1 .0 93 h ssccon 07 h scen ten mstr cpol cpha brs2 brs1 brs0 94 h stb xx h .7 .6 .5 .4 .3 .2 .1 .0 95 h srb xx h .7 .6 .5 .4 .3 .2 .1 .0 96 h sscmod 00 h loopb trio 0 0 0 0 0 lsbsm 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 9a h ien2 x00x- x00x b ? ? ex8 ex7 ? essc ecan ? a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h eal wdt et2 es et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0
c515c data sheet 28 2003-02 aa h srell d9 h .7 .6 .5 .4 .3 .2 .1 .0 ab h scf xxxx- xx00 b ? ? ???? wcoltc ac h scien xxxx- xx00 b ? ? ???? wcentcen b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b1 h syscon 4) x010- xx01 b ? pmod eale rmap ? ? xmap1 xmap0 b1 h syscon 5) x010- x001 b ? pmod eale rmap ? cswo xmap1 xmap0 b8 h 2) ien1 00 h exen2 swdt ex6 ex5 ex4 ex3 ex2 eadc b9 h ip1 0x00- 0000 b pdir ? .5 .4 .3 .2 .1 .0 ba h srelh xxxx- xx11 b ? ? ???? .1 .0 c0 h 2) ircon 00 h exf2 tf2 iex6 iex5 iex4 iex3 iex2 iadc c1 h ccen 00 h coca h3 coca l3 coca h2 coca l2 coca h1 coca l1 coca h0 coca l0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00 h t2ps i3fr i2fr t2r1 t2r0 t2cm t2i1 t2i0 ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 table 5 contents of the sfrs, sfrs in numeric order of their addresses (cont?d) addr. register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c515c data sheet 29 2003-02 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d8 h 2) adcon0 00 h bd clk adex bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1 .0???? ? ? db h p6 ? .7 .6 .5 .4 .3 .2 .1 .0 dc h adcon1 0xxx- x000 b adcl ? ? ? 0 mx2 mx1 mx0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 ff h rxdc txdc int8 sls sto sri sclk adst f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 f8 h 2) p5 ff h .7 .6 .5 .4 .3 .2 .1 .0 f8 h 2) dir5 6) ff h .7 .6 .5 .4 .3 .2 .1 .0 fa h p7 xxxx- xxx1 b ? ? ???? ? int7 fc h vr0 7)8) c5 h 1 1 0001 0 1 fd h vr1 7)8) 95 h 1 0 0101 0 1 fe h vr2 7)8) 02 h 9) 0 0 0000 1 0 1) ?x? means that the value is undefined and the location is reserved. 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. 4) this sfr is available in the c515c-8r and c515c-l. 5) this sfr is available in the c515c-8e. 6) this sfr is a mapped sfr. for accessing this sfr, bit pdir in sfr ip1 must be set. 7) this sfr is a mapped sfr. for accessing this sfr, bit rmap in sfr syscon must be set. 8) these sfrs are read-only registers (c515c-8e only). 9) the content of this sfr varies with the actual step of the c515c-8e (e.g. 01 h for the first step). table 5 contents of the sfrs, sfrs in numeric order of their addresses (cont?d) addr. register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c515c data sheet 30 2003-02 table 6 contents of the can registers in numeric order of their addresses addr. n = 1 to f h 1) regis- ter content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f700 h cr 01 h test cce 0 0 eie sie ie init f701 h sr xx h boff ewrn ? rxok txok lec2 lec1 lec0 f702 h ir xx h intid f704 h btr0 uu h sjw brp f705 h btr1 0uuu. uuuu b 0tseg2 tseg1 f706 h gms0 uu h id28-21 f707 h gms1 uuu1. 1111 b id20-18 11111 f708 h ugml0 uu h id28-21 f709 h ugml1 uu h id20-13 f70a h lgml0 uu h id12-5 f70b h lgml1 uuuu. u000 b id4-0 000 f70c h umlm0 uu h id28-21 f70d h umlm1 uu h id20-18 id17-13 f70e h lmlm0 uu h id12-5 f70f h lmlm1 uuuu. u000 b id4-0 000 f7n0 h mcr0 uu h msgval txie rxie intpnd f7n1 h mcr1 uu h rmtpnd txrq msglst cpuupd newdat f7n2 h uar0 uu h id28-21 f7n3 h uar1 uu h id20-18 id17-13 f7n4 h lar0 uu h id12-5 f7n5 h lar1 uuuu. u000 b id4-0 000 f7n6 h mcfg uuuu. uu00 b dlc dir xtd 0 0 f7n7 h db0n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n8 h db1n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7n9 h db2n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7na h db3n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nb h db4n xx h .7 .6 .5 .4 .3 .2 .1 .0
c515c data sheet 31 2003-02 f7nc h db5n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7nd h db6n xx h .7 .6 .5 .4 .3 .2 .1 .0 f7ne h db7n xx h .7 .6 .5 .4 .3 .2 .1 .0 1) the notation ?n? in the address definition defines the number of the related message object. 2) ?x? means that the value is undefined and the location is reserved. ?u? means that the value is unchanged by a reset operation. ?u? values are undefined (as ?x?) after a power-on reset operation. table 6 contents of the can registers in numeric order of their addresses (cont?d) addr. n = 1 to f h 1) regis- ter content after reset 2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c515c data sheet 32 2003-02 digital i/o ports the c515c allows for digital i/o on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. each port bit consists of a latch, an output driver and an input buffer. read and write accesses to the i/o ports p0 through p7 are performed via their corresponding special function registers p0 to p7. the port structure of port 5 of the c515c is especially designed to operate either as a quasi-bidirectional port structure, compatible to the standard 8051-family, or as a genuine bidirectional port structure. this port operating mode can be selected by software (setting or clearing the bit pmod in the sfr syscon). the output drivers of port 0 and 2 and the in put buffers of port 0 are also used for accessing external memory. in this application, port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. port 2 outputs the high byte of the external memory address when the address is 16 bits wide. otherwise, the port 2 pins continue emitting the p2 sfr contents. analog input ports ports 6 is available as input port only and provides two functions. when used as digital inputs, the corresponding sfr p6 contains the digital value applied to the port 6 lines. when used for analog inputs the desired analog channel is selected by a three-bit field in sfr adcon0 or sfr adcon1. of course, it makes no sense to output a value to these input-only ports by writing to the sfr p6. this will have no effect. if a digital value is to be read, the voltage levels are to be held within the input voltage specifications ( v il / v ih ). since p6 is not bit-addressable, all input lines of p6 are read at the same time by byte instructions. nevertheless, it is possible to use port 6 simultaneously for analog and digital input. however, care must be taken that all bits of p6 that have an undetermined value caused by their analog function are masked.
c515c data sheet 33 2003-02 port structure selection of port 5 after a reset operation of the c515c, the quasi-bidirectional 8051-compatible port structure is selected. for selection of the bidirectional (cmos) port 5 structure the bit pmod of sfr syscon must be set. because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode the direction register dir5 of port 5 must be written. this direction register is mapped to the port 5 register. this means, the port register address is equal to its direction register address. figure 10 illustrates the port and direction register configuration. figure 10 port register, direction register mcs02649 d rq q int. bus, bit 7 write to ip 1 delay: 2.5 machine cycles port register direction register enable pdir enable write to port read port internal bus instruction sequence for the programming of the direction registers: orl ip1, #80h ; set bit pdir write port x direction register with value yyh ; #oyyh dirx, mov
c515c data sheet 34 2003-02 timer / counter 0 and 1 timer / counter 0 and 1 can be used in four operating modes as listed in table 7 : in the ?timer? function (c/ t = ?0?) the register is incremented every machine cycle. therefore the count rate is f osc /6. in the ?counter? function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /12. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 11 illustrates the input clock logic. figure 11 timer/counter 0 and 1 input clock logic table 7 timer/counter 0 and 1 operating modes mode description tmod timer/counter input clock m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 f osc /6 32 f osc /12 32 1 16-bit timer/counter 0 1 f osc /6 f osc /12 2 8-bit timer/counter with 8-bit autoreload 10 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer / timer 1 stops 11 mcs03117 1 & osc c/t = 0 c/t = 1 control =1 6 tr1 p3.5/t1 (tmod) p3.2/int0 f timer 0/1 input clock osc /6 p3.4/t0 tr0 gate p3.3/int1 _ <
c515c data sheet 35 2003-02 timer / counter 2 with compare/capture/reload the timer 2 of the c515c provides additional compare/capture/reload features, which allow the selection of the following operating modes: compare: up to 4 pwm signals with 16-bit/600 ns resolution capture: up to 4 high speed capture inputs with 600 ns resolution reload: modulation of timer 2 cycle time the block diagram in figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. the i/o pins which can used for timer 2 control are located as multifunctional port functions at port 1. figure 12 timer 2 block diagram mcb02730 comparator ccl3/cch3 capture input/ output control p1.0/ int3/ cc0 cc1 int4/ p1.1/ cc2 int5/ p1.2/ cc3 int6/ p1.2/ ccl2/cch2 comparator ccl1/cch1 comparator crcl/crch comparator bit 16 16 bit 16 bit 16 bit osc 6 12 f osc t2ps sync. p1.7/ t2 t2ex p1.5/ sync. & t2i1 t2i0 timer 2 th2 tl2 tf2 reload exen2 reload 1 exf2 interrupt request compare _ <
c515c data sheet 36 2003-02 timer 2 operating modes the timer 2, which is a 16-bit-wide register, ca n operate as timer, event counter, or gated timer. a roll-over of the count value in tl2/th2 from all 1?s to all 0?s sets the timer overflow flag tf2 in sfr ircon, which can generate an interrupt. the bits in register t2con are used to control the timer 2 operation. timer mode: in timer function, the count rate is derived from the oscillator frequency. a prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. gated timer mode: in gated timer function, the external input pin t2 (p1.7) functions as a gate to the input of timer 2. if t2 is high, the internal clock input is gated to the timer. t2 = 0 stops the counting procedure. this facilitates pulse width measurements. the external gate signal is sampled once every machine cycle. event counter mode: in the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin t2 (p1.7). in this function, the external input is sampled every machine cycle. since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. reload of timer 2: two reload modes are selectable: in mode 0, when timer 2 rolls over from all 1?s to all 0?s, it not only sets tf2 but also causes the timer 2 registers to be loaded with the 16-bit value in the crc register, which is preset by software. in mode 1, a 16-bit reload from the crc register is caused by a negative transition at the corresponding input pin p1.5/t2ex. this transition will also set flag exf2 if bit exen2 in sfr ien1 has been set.
c515c data sheet 37 2003-02 timer 2 compare modes the compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. compare mode 0 in compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. as long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. figure 13 shows a functional diagram of a port circuit when used in compare mode 0. the port latch is directly controlled by the timer overflow and compare match signals. the input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. figure 13 port latch in compare mode 0 mcs02661 latch port q q clk d port pin read pin dd v read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match s r overflow timer 16 bit bit 16
c515c data sheet 38 2003-02 compare mode 1 if compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. in compare mode 1 (see figure 14 ) the port circuit consists of two separate latches. one latch (which acts as a ?shadow latch?) can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. figure 14 compare function in compare mode 1 mcs02662 latch port q q clk d read pin dd v d clk q shadow latch read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match pin port 16 bit 16 bit
c515c data sheet 39 2003-02 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 8 . for clarification some terms regarding the difference between ?baud rate clock? and ?baud rate? should be mentioned. in the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators/timers have to provide a ?baud rate clock? (output signal in figure 15 to the serial interface which - there divided by 16 - results in the actual ?baud rate?. further, the abbreviation f osc refers to the oscillator frequency (crystal or external clock operation). the variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a dedicated baud rate generator (see figure 15 ). table 8 usart operating modes mode scon description sm0 sm1 000 shift register mode, fixed baud rate serial data enters and exits through r d; t d outputs the shift clock; 8-bit are transmitted/received (lsb first) 101 8-bit uart, variable baud rate 10 bits are transmitted (through t d) or received (at r d) 210 9-bit uart, fixed baud rate 11 bits are transmitted (through t d) or received (at r d) 311 9-bit uart, variable baud rate like mode 2
c515c data sheet 40 2003-02 figure 15 block diagram of baud rate generation for the serial interface table 9 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits bd and smod. table 9 serial interface - baud rate dependencies serial interface operating modes active control bits baud rate calculation bd smod mode 0 (shift register) ?? f osc / 6 mode 1 (8-bit uart) mode 3 (9-bit uart) 0 x controlled by timer 1 overflow: (2 smod timer 1 overflow rate) / 32 1 x controlled by baud rate generator (2 smod f osc ) / (32 baud rate generator overflow rate) mode 2 (9-bit uart) ? 0 1 f osc / 32 f osc / 16 mcs02733 rate f osc (smod) baud clock pcon.7 2 (sm0/ sm1) scon.7 scon.6 only one mode can be selected adcon0.7 (bd) 0 1 0 1 baud rate generator (srelh srell) timer 1 mode 2 mode 0 note: the switch configuration shows the reset state. mode 3 mode 1 overflow 6
c515c data sheet 41 2003-02 ssc interface the c515c microcontroller provides a synchronous serial channel unit, the ssc. this interface is compatible to the popular spi serial bus interface. figure 16 shows the block diagram of the ssc. the central element of the ssc is an 8-bit shift register. the input and the output of this shift register are each connected via a control logic to the pin p4.2 / sri (ssc receiver in) and p4.3 / sto (ssc transmitter out). this shift register can be written to (sfr stb) and can be read through the receive buffer register srb. figure 16 ssc block diagram the ssc has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. the clock signal is fully programmable for clock polarity and phase. the pin used for the clock signal is p4.1 / sclk. when operating in slave mode, a slave select input is provided which enables the ssc interface and also will control the transmitter output. the pin used for this is p4.4 / sls . the ssc control block is responsible for controlling the different modes and operation of the ssc, checking the status, and generating the respective status and interrupt signals. mcb02735 p4.1/sclk p4.2/sri p4.3/sto p4.4/sls pin control logic shift register receive buffer register stb clock selection clock divider srb f osc control register status register int. enable reg. scien ssccon scf control logic internal bus interrupt
c515c data sheet 42 2003-02 can controller the on-chip can controller is the functional heart which provides all resources that are required to run the standard can protocol (11-bit identifiers) as well as the extended can protocol (29-bit identifiers). it provides a sophisticated object layer to relieve the cpu of as much overhead as possible when controlling many different message objects (up to 15). this includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. in order to implement the physical layer, external components have to be connected to the c515c. the internal bus interface connects the on-chip can controller to the internal bus of the microcontroller. the registers and data locations of the can interface are mapped to a specific 256 bytes wide address range of the external data memory area (f700 h to f7ff h ) and can be accessed using movx instructions. figure 17 shows a block diagram of the on-chip can controller.
c515c data sheet 43 2003-02 figure 17 can controller block diagram the tx/rx shift register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the intelligent memory. the bit stream processor (bsp) is a sequencer controlling the sequential data stream between the tx/rx shift register, the crc register, and the bus line. the bsp also controls the eml and the parallel data stream between the tx/rx shift register and the intelligent memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the can protocol. note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the bsp. mcb02736 bit timing logic timing generator btl-configuration crc gen./check tx/rx shift register txdc rxdc intelligent interrupt register memory processor register status stream bit error logic management messages handlers control status + to internal bus clocks control messages (to all)
c515c data sheet 44 2003-02 the cyclic redundancy check register (crc) generates the cyclic redundancy check code to be transmitted after the data bytes and checks the crc code of incoming messages. this is done by dividing the data stream by the code generator polynomial. the error management logic (eml) is responsible for the fault confinement of the can device. its counters, the receive error counter and the transmit error counter, are incremented and decremented by commands from the bit stream processor. according to the values of the error counters, the can controller is set into the states error active , error passive and busoff. the bit timing logic (btl) monitors the busline input rxdc and handles the busline related bit timing according to the can protocol. the btl synchronizes on a recessive to dominant busline transition at start of frame (hard synchronization) and on any further recessive to dominant busline transition, if the can controller itself does not transmit a dominant bit (resynchronization). the btl also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the sample point in the bit time. the programming of the btl depends on the baudrate and on external physical delay times. the intelligent memory (cam/ram array) provides storage for up to 15 message objects of maximum 8 data bytes length. each of these objects has a unique identifier and its own set of control and status bits. after the initial configuration, the intelligent memory can handle the reception and transmission of data without further cpu actions. switch-off capability of the can controller (c515c-8e only) for power consumption reasons, the on-chip can controller in the c515c-8e can be switched off by setting bit cswo (bit 2) in sfr syscon. when the can controller is switched off its clock signal is turned off and the operation of the can controller is stopped. this switch-off state of the can controller is equal to its state in software power down mode. after clearing bit cswo again the can controller has to be reconfigured.
c515c data sheet 45 2003-02 10-bit a/d converter the c515c includes a high performance / high speed 10-bit a/d-converter (adc) with 8 analog input channels. it operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the a/d converter provides the following features: 8 multiplexed input channels (port 6), which can also be used as digital inputs 10-bit resolution single or continuous conversion mode internal or external start-of-conversion trigger capability interrupt request generation after each conversion using successive approximation conversion technique via a capacitor array built-in hidden calibration of offset and linearity errors the main functional blocks of the a/d converter are shown in figure 19 . the a/d converter uses basically two clock signals for operation: the input clock f in (= 1/ t in ) and the conversion clock f adc (= 1/ t adc ). these clock signals are derived from the c515c system clock f osc which is applied at the xtal pins. the input clock f in is equal to f osc . the conversion clock is limited to a maximum frequency of 2 mhz and therefore must be adapted to f osc by programming the conversion clock prescaler. the table in figure 18 shows the prescaler ratios and the resulting a/d conversion times which must be selected for typical system clock rates.
c515c data sheet 46 2003-02 figure 18 a/d converter clock selection mcu system clock rate ( f osc ) adcl conversion clock f adc [mhz] 2 mhz 0 .5 4 mhz 0 1 6 mhz 0 1.5 8 mhz 0 2 10 mhz 1 1.25 mcs02748 mux adcl osc f clock prescaler conversion clock f adc input clock in f a/d converter conditions: f adc max 2 mhz f in = f osc = 1 clp 4 8 _ <
c515c data sheet 47 2003-02 figure 19 a/d converter block diagram input clock clock conversion s & h conversion start of shaded bit locations are not used in adc-functions. write to addatl p4.0/adst agnd osc aref v v f port 6 mux conversion clock prescaler ircon (c0 ) adcon0 (d8 ) adcon1 (dc ) adcl bd h p6 (db ) p6.7 exf2 adex clk h -- bsy - p6.5 iex6 h p6.6 tf2 h p6.4 iex5 swdt ien1 (b8 ) h exen2 ex6 ex5 single/ h h converter continuous a/d f in adc f mode msb .8 .7 .6 .1 lsb - - .5 .4 .3 .2 - - - - mcb02747 bus internal addatl (da ) mx2 mx2 adm - mx1 mx1 iex3 p6.2 p6.3 iex4 p6.1 iex2 addath (d9 ) mx0 mx0 p6.0 iadc ex3 ex4 ex2 eadc bus internal
c515c data sheet 48 2003-02 interrupt system the c515c provides 17 interrupt sources with four priority levels. seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, a/d converter, ssc interface, can controller), and ten interrupts may be triggered externally (p1.5/t2ex, p3.2/int0 , p3.3/int1, p1.4/int2, p1.0/int3 , p1.1/int4, p1.2/int5, p1.3/int6, p7.0/int7 , p4.5/int8 ). the wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin p3.2/int0 . in the c515c the 17 interrupt sources are combined to six groups of two or three interrupt sources. each interrupt group can be programmed to one of the four interrupt priority levels. figure 20 to figure 22 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.
c515c data sheet 49 2003-02 figure 20 interrupt request sources (part 1) polling sequence h ecan ie error can controller interrupt sources note: each of the 15 can controller message objects provides the bits/flags in the shaded area. ien0.7 cleared by hardware request flag is receive int2 p1.4/ t2con.5 bit addressable i2fr rxie mcr0.5/4 message transmit message txie mcr0.3/2 cr.3 eie ien1.1 iex2 ircon.1 ex2 eal h 004b ien2.1 intpnd mcr0.0/1 1 < _ cr.1 see note mcs02752 ip1.1 ip0.1 0003 int0 overflow status timer 0 cr.2 sie a/d converter tcon.0 it0 ien0.1 _ < 1 tcon.5 tf0 008b et0 h 000b ien0.0 eadc ien1.0 iadc ircon.0 tcon.1 h 0043 ex0 h p3.2/ ie0 priority level ip1.0 ip0.0 lowest highest priority level
c515c data sheet 50 2003-02 figure 21 interrupt request sources (part 2) mcs02753 bit addressable request flag is cleared by hardware ip1.2 h 0013 tcon.3 ien0.2 ie1 ex1 p3.3/ it1 tcon.2 essc ien2.2 0093 h scf.1 wcol tc scf.0 ssc ip0.2 highest priority level 0053 h ip1.3 ip0.3 timer 1 h 001b tcon.7 ien0.3 tf1 et1 overflow int1 int4/ p1.1/ ex4 iex4 ien1.3 ircon.3 005b h cc1 lowest priority level eal ien0.7 polling sequence 1 t2con.6 i3fr ex3 iex3 ien1.2 ircon.2 cc0 p1.0/ int3/ inerface scien.1 wcen tcen scien.0 _ <
c515c data sheet 51 2003-02 figure 22 interrupt request sources (part 3) mcs02754 bit addressable request flag is cleared by hardware ip1.4 h 0023 es ien0.4 00a3 h scon.0 ri ti scon.1 usart ip0.4 highest priority level ex5 iex5 ien1.4 ircon.4 0063 h ip1.5 ip0.5 timer 2 h 00ab overflow 006b h lowest priority level eal ien0.7 polling sequence ien2.4 ex7 cc2 p1.2/ int5/ ircon.7 exf2 tf2 ircon.6 ien0.5 et2 002b h exen2 ien1.7 p1.5/ t2ex int6/ p1.3/ cc3 ex8 ien2.5 ircon.5 ien1.5 iex6 ex6 1 1 int7 p7.0/ p4.5/ int8 _ < _ <
c515c data sheet 52 2003-02 table 10 interrupt source and vectors interrupt source interrupt vector address interrupt request flags external interrupt 0 0003 h ie0 timer 0 overflow 000b h tf0 external interrupt 1 0013 h ie1 timer 1 overflow 001b h tf1 serial channel 0023 h ri / ti timer 2 overflow / ext. reload 002b h tf2 / exf2 a/d converter 0043 h iadc external interrupt 2 004b h iex2 external interrupt 3 0053 h iex3 external interrupt 4 005b h iex4 external interrupt 5 0063 h iex5 external interrupt 6 006b h iex6 wake-up from power-down mode 007b h ? can controller 008b h ? external interrupt 7 00a3 h ? external interrupt 8 00ab h ? ssc interface 0093 h tc / wcol
c515c data sheet 53 2003-02 fail save mechanisms the c515c offers two on-chip peripherals which monitor the program flow and ensure an automatic ?fail-safe? reaction for cases where the controller?s hardware fails or the software hangs up: a programmable watchdog timer (wdt) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 6 mhz. an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. programmable watchdog timer the watchdog timer in the c515c is a 15-bit timer, which is incremented by a count rate of f osc /12 up to f osc /192. for programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. figure 23 shows the block diagram of the watchdog timer unit. figure 23 block diagram of the programmable watchdog timer the watchdog timer can be started by software (bit swdt) or by hardware through pin pe /swd, but it cannot be stopped during active mode of the c515c. if the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. for refreshing of the watchdog timer the content of the sfr wdtrel is transferred to the upper 7-bit of the watchdog timer. the refresh sequence consists of mcb02755 control logic pe/swd external hw power-down wdt reset request 14 8 wdth wdtrel (86 ) 0 7 6 ien1 (b8 ) ien0 (a8 ) h h 07 wdtl ip0 (a9 ) h wdt swdt - - - - - - - - - - - - - - h external hw reset -- - - - - - wdts wdtpsel 16 /6 osc f 2
c515c data sheet 54 2003-02 two consecutive instructions which set the bits wdt and swdt each. the reset cause (external reset or reset caused by the watchdog) can be examined by software (flag wdts). it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. oscillator watchdog the oscillator watchdog unit serves for four functions: monitoring of the on-chip oscillator?s function the watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the rc oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. restart from the hardware power down mode if the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. the oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. control of external wake-up from software power-down mode when the software power-down mode is left by a low level at the p3.2/int0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. in the power-down mode the rc oscillator and the on-chip oscillator are stopped. both oscillators are started again when power-down mode is released. when the on-chip oscillator has a higher frequency than the rc oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
c515c data sheet 55 2003-02 figure 24 block diagram of the oscillator watchdog owds 1 ip0 (a9 ) frequency comparator delay f 2 < 1 f f 1 2 f internal clock on-chip oscillator oscillator rc rc f 3 mhz mcb02757 h start/ stop stop start/ control logic xtal1 xtal2 p3.2/ int0 logic control ewpd (pcon1.7) mode activated power-down power-down mode wake-up interrupt reset internal 5 2 _ <
c515c data sheet 56 2003-02 power saving modes the c515c provides two basic power saving modes, the idle mode and the power down mode. additionally, a slow down mode is available. this power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. idle mode the cpu is gated off from the oscillator. all peripherals are still provided with the clock and are able to work. idle mode is entered by software and can be left by an interrupt or reset. power down mode the operation of the c515c is completely stopped and the oscillator is turned off. this mode is used to save the contents of the internal ram with a very low standby current. software power down mode: software power down mode is entered by software and can be left by reset or by a short low pulse at pin p3.2/int0 (or p4.7/rxdc , c515c-8e only). hardware power down mode: hardware power down mode is entered when the pin hwpd is put to low level. slow-down mode the controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. this slows down all parts of the controller, the cpu and all peripherals, to 1/32 th of their normal operating frequency. slowing down the frequency significantly reduces power consumption. the slow down mode can be combined with the idle mode. table 11 gives a general overview of the entry and exit conditions of the power saving modes. in the power down mode of operation, v dd can be reduced to minimize power consumption. it must be ensured, however, that v dd is not reduced before the power down mode is invoked, and that v dd is restored to its normal operating level, before the power down mode is terminated. if e.g. the idle mode is left through an interrupt, the microcontroller state (cpu, ports, peripherals) remains preserved. if a power saving mode is left by a hardware reset, the microcontroller state is disturbed and replaced by the reset state of the c515c. if ws (bit 4) is sfr pcon1 is set (c515c-8e only), pin p4.7/rxdc is alternatively selected as wake-up pin for the software power down mode. if ws (bit 4) is sfr pcon1 is cleared (c515c-8e only), pin p3.2/int0 is selected as wake-up pin for the software power down mode. for the c515c-8r, p3.2/int0 is always selected as wake-up pin.
c515c data sheet 57 2003-02 table 11 power saving modes overview mode entering (2-instruction example) leaving by remarks idle mode orl pcon, #01 h orl pcon, #20 h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock hardware reset software power-down mode orl pcon, #02 h orl pcon, #40 h hardware reset oscillator is stopped; contents of on-chip ram and sfr?s are maintained; short low pulse at pin p3.2/int0 (or p4.7/rxdc , c515c-8e only) hardware power-down mode hwpd = low hwpd = high c515c is put into its reset state and the oscillator is stopped; ports become floating outputs slow down mode orl pcon, #10 h anl pcon, #0ef h or hardware reset oscillator frequency is reduced to 1/32 of its nominal frequency
c515c data sheet 58 2003-02 otp memory operation (c515c-8e only) the c515c-8e contains a 64 kbytes one-time programmable (otp) program memory. with the c515c-8e fast programming cycles are achieved (1 byte in 100 s). also several levels of otp memory protection can be selected. for programming of the device, the c515c-8e must be put into the programming mode. this typically is done not in-system but in a special programming hardware. in the programming mode the c515c-8e operates as a slave device similar as an eprom standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 v programming voltage. figure 25 shows the pins of the c515c-8e which are required for controlling of the otp programming mode. figure 25 programming mode configuration of the c515c-8e mcp03651 v ss dd v a0-7 a8-a15 pale pmsel0 pmsel1 xtal1 xtal2 p0-7 ea/ prog prd reset psen psel pp v port 2 port 0 c515c-8e
c515c data sheet 59 2003-02 c515c-8e pin configuration in programming mode figure 26 p-mqfp-80-1 pin configuratio n of the c515c-8e in programming mode (top view) mcp03652 1234567891011 n.c. 12 13 14 15 16 17 18 19 20 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 a2/a10 ss v ss v n.c. pale prd psel pmsel1 pmsel0 n.c. reset v ss a3/a11 a4/a12 a5/a13 a6/a14 a7/a15 n.c. psen prog ea/ d0 d1 d2 d3 d4 d5 d6 d7 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40 61 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. ss v dd v dd v n.c. v pp a1/a9 a0/a8 xtal1 xtal2 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. v dd dd v n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. c515c-8e n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. v ss v dd n.c. n.c.
c515c data sheet 60 2003-02 the following table 12 contains the functional description of all c515c-8e pins which are required for otp memory programming. table 12 pin definitions and functions in programming mode symbol pin number i/o 1) function reset 1i reset this input must be at static ?0? (active) level during the whole programming mode. pmsel0 pmsel1 15 16 i i programming mode selection pins these pins are used to select the different access modes in programming mode. pmsel1,0 must satisfy a setup time to the rising edge of pale. when the logic level of pmsel1,0 is changed, pale must be at low level. psel 17 i basic programming mode select this input is used for the basic programming mode selection and must be switched according figure 27 . prd 18 i programming mode read strobe this input is used for read access control for otp memory read, version byte read, and lock bit read operations. pale 19 i programming address latch enable pale is used to latch the high address lines. the high address lines must satisfy a setup and hold time to/from the falling edge of pale. pale must be at low level whenever the logic level of pmsel1,0 is changed. xtal2 36 i xtal2 input to the oscillator amplifier. xtal1 37 o xtal1 output of the inverting oscillator amplifier. pmsel1 pmsel0 access mode 00reserved 0 1 read version bytes 1 0 program/read lock bits 1 1 program/read otp memory byte
c515c data sheet 61 2003-02 a0/a8 - a7/a15 38 - 45 i address lines p2.0-7 are used as multiplexed address input lines a0-a7 and a8-a15. a8-a15 must be latched with pale. psen 47 i program store enable this input must be at static ?0? level during the whole programming mode. prog 48 i programming mode write strobe this input is used in programming mode as a write strobe for otp memory program and lock bit write operations. during basic programming mode selection a low level must be applied to prog . ea / v pp 49 i external access / programming voltage this pin must be at 11.5 v ( v pp ) voltage level during programming of an otp memory byte or lock bit. during an otp memory read operation this pin must be at high level ( v ih ). this pin is also used for basic programming mode selection. at basic programming mode selection a low level must be applied to ea / v pp . d0 - 7 52 - 58 i/o data lines 0-7 during programming mode, data bytes are read or written from or to the c515c-8e via the bidirectional d0-7 which are located at port 0. v ss 13, 34, 35, 51, 70 ? circuit ground potential must be applied to these pins in programming mode. v dd 14, 32, 33, 50, 69 ? power supply terminal must be applied to these pins in programming mode. n.c. 2-12, 20-31, 46, 60-67, 69, 71-80 ? not connected these pins should not be connected in programming mode. 1) i = input; o = output table 12 pin definitions and functions in programming mode (cont?d) symbol pin number i/o 1) function
c515c data sheet 62 2003-02 c515c-8e basic programming mode selection the basic programming mode selection scheme is shown in figure 27 . figure 27 c515c-8e basic programming mode selection mct03653 "0" (xtal1/xtal2) clock v dd reset "0" psen 0.1 pmsel1, 0 "0" prog "1" prd psel "0" pale ea/ v pp pp v ih v are not actively driven during this period signals ready for access mode selection 5 v 0 v stable
c515c data sheet 63 2003-02 c515c-8e lock bits programming / read the c515c-8e has two programmable lock bits which, when programmed according table 14 , provide four levels of protection for the on-chip otp code memory. the state of the lock bits can also be read. table 13 access modes selection access mode ea / v pp prog prd pmsel address (port 2) data (port 0) 10 program otp memory byte v pp h hha0-7 a8-15 d0-7 read otp memory byte v ih h program otp lock bits v pp hhl? d1, d0 see table 14 read otp lock bits v ih h read otp version byte v ih h l h byte addr. of version byte d0-7
c515c data sheet 64 2003-02 table 14 lock bit protection types lock bits at d1, d0 protection level protection type d1 d0 1 1 level 0 the otp lock feature is disabled. during normal operation of the c515c-8e, the state of the ea pin is not latched on reset. 1 0 level 1 during normal operation of the c515c-8e, movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset. an otp memory read operation is only possible according to rom verification mode 2, as it is defined for a protected rom version of the c515c-8r. further programming of the otp memory is disabled (reprogramming security). 0 1 level 2 same as level 1, but also otp memory read operation using rom verification mode 2 is disabled. 0 0 level 3 same as level 2; but additionally external code execution by setting ea = low during normal operation of the c515c-8e is no more possible. external code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the rom boundary), is still possible.
c515c data sheet 65 2003-02 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c? voltage on v dd pins with respect to ground ( v ss ) v dd -0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v dd + 0.5 v ? input current on any pin during overload condition ? -10 10 ma ? absolute sum of all input currents during overload condition ?? |100ma|ma? power dissipation p diss ?1 w?
c515c data sheet 66 2003-02 operating conditions parameter symbol limit values unit notes min. max. supply voltage v dd 4.25 5.5 v active mode, f oscmax = 10 mhz 2 5.5 v power down mode ground voltage v ss 0 v reference voltage ambient temperature: c? sab-c515c t a 070 saf-c505 t a -40 85 sah-c505 t a -40 110 analog reference voltage v aref 4 v dd + 0.1 v ? analog ground voltage v agnd v ss - 0.1 v ss + 0.2 v ? analog input voltage v ain v agnd v aref v? xtal clock f osc 210mhz?
c515c data sheet 67 2003-02 dc characteristics (operating conditions apply) parameter sym- bol limit values unit test condition min. max. input low voltages all except ea , reset , hwpd ea pin reset and hwpd pins port 5 in cmos mode v il v il1 v il2 v ilc -0.5 -0.5 -0.5 -0.5 0.2 v dd - 0.1 0.2 v dd - 0.3 0.2 v dd + 0.1 0.3 v dd v? input high voltages all except xtal2, reset , and hwpd ) xtal2 pin reset and hwpd pins port 5 in cmos mode v ih v ih1 v ih2 v ihc 0.2 v dd + 0.9 0.7 v dd 0.6 v dd 0.7 v dd v dd + 0.5 v dd + 0.5 v dd + 0.5 v dd + 0.5 v? output low voltages ports 1, 2, 3, 4, 5, 7 (incl. cmos) port 0, ale, psen , cpur p4.1, p4.3 in push-pull mode v ol v ol1 v ol3 ? ? ? 0.45 0.45 0.45 v i ol = 1.6 ma 1) i ol = 3.2 ma 1) i ol = 3.75 ma 1) output high voltages ports 1, 2, 3, 4, 5, 7 port 0 in external bus mode, ale, psen , cpur port 5 in cmos mode p4.1, p4.3 in push-pull mode v oh v oh2 v ohc v oh3 2.4 0.9 v dd 2.4 0.9 v dd 0.9 v dd 0.9 v dd ? ? ? ? ? ? v i oh = -80 a i oh = -10 a i oh = -800 a i oh = -80 a 2) i oh = -800 a i oh = -833 a logic 0 input current ports 1, 2, 3, 4, 5, 7 i il -10 -70 a v in = 0.45 v logical 0-to-1 transition current ports 1, 2, 3, 4, 5, 7 i tl -65 -650 a v in = 2 v input leakage current port 0, ea , p6, hwpd , ain0-7 i li ? 1 a0.45 < v in < v dd input low current to reset for reset xtal2 pe /swd i li2 i li3 i li4 ? ? ? -100 -15 -20 a v in = 0.45 v v in = 0.45 v v in = 0.45 v pin capacitance c io ?10pf f c = 1 mhz, t a = 25 c overload current i ov ? 5ma 3)4) programming voltage v pp 10.9 12.1 v 11.5 v 5%
c515c data sheet 68 2003-02 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address lines are stabilizing. 3) overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all port pins may not exceed 50 ma . the supply voltage ( v dd and v ss ) must remain within the specified limits. 4) not 100% tested, guaranteed by design characterization.
c515c data sheet 69 2003-02 power supply current parameter sym- bol limit values unit test condition typ. 1) 1) the typical i dd values are periodically measured at t a = +25 c and v dd = 5 v but not 100% tested. max. 2) 2) the maximum i dd values are measured under worst case conditions ( t a = 0 c or -40 c and v dd = 5.5 v) active mode c515c-8r/ c515c-lm 6 mhz 10 mhz i dd 11.97 18.81 13.74 21.10 ma 3) 3) i dd (active mode) is measured with: xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v dd - 0.5 v; xtal1 = n.c.; ea = pe /swd = port 0 = port 6 = v dd ; hwpd = v dd ; reset = v ss ; all other pins are disconnected. c515c-8e 6 mhz 10 mhz i dd 11.3 17.66 12.94 20.10 ma idle mode c515c-8r/ c515c-lm 6 mhz 10 mhz i dd 6.9 10.46 7.87 11.87 ma 4) 4) i dd (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v dd - 0.5 v; xtal1 = n.c.; reset = v dd ; ea = v ss ; port0 = v dd ; all other pins are disconnected; c515c-8e 6 mhz 10 mhz i dd 3.95 4.71 4.70 5.50 ma active mode with slow-down enabled c515c-8r/ c515c-lm 6 mhz 10 mhz i dd 4.06 4.62 5.03 5.75 ma 5) 5) i dd (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v dd - 0.5 v; xtal1 = n.c.; reset = v dd ; all other pins are disconnected; the microcontroller is put into slow-down mode by software. c515c-8e 6 mhz 10 mhz i dd 4.01 4.65 4.77 5.53 ma idle mode with slow-down enabled c515c-8r/ c515c-lm 6 mhz 10 mhz i dd 3.54 3.86 4.46 4.90 ma 6) c515c-8e 6 mhz 10 mhz i dd 3.62 4.14 4.21 4.77 ma power-down mode c515c-8r/ c515c-lm i pd 26 42.9 a v dd = 2 ? 5.5 v 7) c515c-8e i pd 11.14 30 a at ea / v pp in programming mode c515c-8e i ddp ?30ma?
c515c data sheet 70 2003-02 6) i dd (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v dd - 0.5 v; xtal1 = n.c.; reset = v dd ; ea = v ss ; port0 = v dd ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software. 7) i pd (power-down mode) is measured under following conditions: ea = reset = port 0 = port 6 = v dd ; xtal1 = n.c.; xtal2 = v ss ; pe /swd = v ss ; hwpd = v dd ; v agnd = v ss ; v aref = v dd ; all other pins are disconnected. i pd (hardware power-down mode) is independent of any particular pin connection.
c515c data sheet 71 2003-02 power supply current calculation formulas note: f osc is the oscillator frequency in mhz. i dd values are given in ma. parameter symbol formula active mode c515c-8r/ c515c-lm i dd typ i dd max 1.71 f osc + 1.71 1.84 f osc + 2.7 c515c-8e i dd typ i dd max 1.59 f osc + 1.76 1.79 f osc + 2.2 idle mode c515c-8r/ c515c-lm i dd typ i dd max 0.89 f osc + 1.56 1.00 f osc + 1.87 c515c-8e i dd typ i dd max 0.19 f osc + 2.81 0.20 f osc + 3.5 active mode with slow-down enabled c515c-8r/ c515c-lm i dd typ i dd max 0.14 f osc + 3.22 0.18 f osc + 3.95 c515c-8e i dd typ i dd max 0.16 f osc + 3.05 0.19 f osc + 3.63 idle mode with slow-down enabled c515c-8r/ c515c-lm i dd typ i dd max 0.08 f osc + 3.06 0.11 f osc + 3.8 c515c-8e i dd typ i dd max 0.13 f osc + 2.84 0.14 f osc + 3.37
c515c data sheet 72 2003-02 figure 28 i dd diagrams of c515c-8r/c515c-lm f osc [mhz] 6 4 2 10 5 10 20 [ma] 15 8 i d l e m o d e 25 a c t i v e m o d e a c t i v e m o d e i d l e m o d e i d l e + s l o w - d o w n s l o w - d o w n m o d e i dd max i dd typ c515c-8e c515c-lm
c515c data sheet 73 2003-02 figure 29 i dd diagrams of c515c-8e c515c-8e f osc [mhz] 6 4 2 10 5 10 20 [ma] 15 8 25 i d l e m o d e + s l o w - d o w n a c t i v e m o d e idl e mod e a c t i v e m o d e + s l o w - d o w n i dd max i dd typ
c515c data sheet 74 2003-02 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. sample time t s ?16 t in 8 t in ns prescaler 8 prescaler 4 2) 2) during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. conversion cycle time t adcc ?96 t in 48 t in ns prescaler 8 prescaler 4 3) 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. total unadjusted error t ue ? 2lsb 4) 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v dd = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. internal resistance of reference voltage source r aref ? t adc / 250 - 0.25 k ? t adc in [ns] 5)6) 5) during the conversion the adc?s capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization. internal resistance of analog source r asrc ? t s / 500 - 0.25 k ? t s in [ns] 2)6) adc input capacitance c ain ?50pf 6)
c515c data sheet 75 2003-02 clock calculation table further timing conditions: t adc min = 500 ns t in = 1 / f osc = t clp clock prescaler ratio adcl t adc t s t adcc 818 t in 16 t in 96 t in 404 t in 8 t in 48 t in
c515c data sheet 76 2003-02 ac characteristics (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics parameter symbol limit values unit 10-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp = 2 mhz to 10 mhz min. max. min. max. ale pulse width t lhll 60 ? clp - 40 ? ns address setup to ale t avll 15 ? tcl hmin - 25 ? ns address hold after ale t llax 15 ? tcl hmin - 25 ? ns ale to valid instruction in t lliv ? 113 ? 2 clp - 87 ns ale to psen t llpl 20 ? tcl lmin - 20 ? ns psen pulse width t plph 115 ? clp + tcl hmin - 30 ?ns psen to valid instruction in t pliv ?75? clp + tcl hmin - 65 ns input instruction hold after psen t pxix 0?0 ? ns input instruction float after psen t pxiz 1) 1) interfacing the c515c to devices with float times up to 35 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. ?30? tcl lmin - 10 ns address valid after psen t pxav 1) 35 ? tcl lmin - 5 ? ns address to valid instruction in t aviv ? 180 ? 2 clp + tcl hmin - 60 ns address float to psen t azpl 00?ns
c515c data sheet 77 2003-02 external data memory characteristics parameter symbol limit values unit 10-mhz clock duty cycle 0.4 to 0.6 variable clock 1/clp= 2 mhz to 10 mhz min. max. min. max. rd pulse width t rlrh 230 ? 3 clp - 70 ? ns wr pulse width t wlwh 230 ? 3 clp - 70 ? ns address hold after ale t llax2 48 ? clp - 15 ? ns rd to valid data in t rldv ?150? 2 clp + tcl hmin - 90 ns data hold after rd t rhdx 0?0 ? ns data float after rd t rhdz ? 80 ? clp - 20 ns ale to valid data in t lldv ? 267 ? 4 clp - 133 ns address to valid data in t avdv ?285? 4 clp + tcl hmin - 155 ns ale to wr or rd t llwl 90 190 clp + tcl lmin - 50 clp + tcl lmin + 50 ns address valid to wr t avwl 103 ? 2 clp - 97 ? ns wr or rd high to ale high t whlh 15 65 tcl hmin - 25 tcl hmin + 25 ns data valid to wr transition t qvwx 5?tcl lmin - 35 ? ns data setup before wr t qvwh 218 ? 3 clp + tcl lmin - 122 ?ns data hold after wr t whqx 13 ? tcl hmin - 27 ? ns address float after rd t rlaz ?0? 0 ns
c515c data sheet 78 2003-02 note: the 10 mhz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. ssc interface characteristics parameter symbol limit values unit min. max. clock cycle time: master mode slave mode t sclk t sclk 0.4 1.0 ? ? s s clock high time t sch 360 ? ns clock low time t scl 360 ? ns data output delay t d ? 100 ns data output hold t ho 0?ns data input setup t s 100 ? ns data input hold t hi 100 ? ns tc bit set delay t dtc ?8 clpns external clock drive at xtal2 parameter symbol cpu clock = 10 mhz duty cycle 0.4 to 0.6 variable cpu clock 1/clp = 2 to 10 mhz unit min. max. min. max. oscillator period clp 100 100 100 500 ns high time tcl h 40 ? 40 clp - tcl l ns low time tcl l 40 ? 40 clp - tcl h ns rise time t r ?12? 12 ns fall time t f ?12? 12 ns oscillator duty cycle dc 0.4 0.6 40 / clp 1 - 40 / clp ? clock cycle tcl 40 60 clp dc min clp dc max ns
c515c data sheet 79 2003-02 figure 30 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
c515c data sheet 80 2003-02 figure 31 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
c515c data sheet 81 2003-02 figure 32 data memory write cycle figure 33 external clock drive at xtal2 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph mct02704 xtal2 tclh tcll t r clp f t v ih2 il v
c515c data sheet 82 2003-02 figure 34 ssc timing notes: 1. shown is the data/clock relationship for cpol = cpha = 1. the timing diagram is valid for the other cases accordingly. 2. in the case of slave mode and cpha = 0, the output delay for the msb applies to the falling edge of sls (if transmitter is enabled). 3. in the case of master mode and cpha = 0, the msb becomes valid after the data has been written into the shift register, i.e. at least one half sclk clock cycle before the first clock transition. mct02417 sclk sto sri tc t scl msb lsb msb lsb sch t t sclk s t hi t ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d tt hd dtc t
c515c data sheet 83 2003-02 otp memory programming mode characteristics v dd = 5 v 10%; v pp = 11.5 v 5%; t a = 25 c 10 c parameter symbol limit values unit min. max. ale pulse width t paw 35 ? ns pmsel setup to ale rising edge t pms 10 ? ns address setup to ale, prog , or prd falling edge t pas 10 ? ns address hold after ale, prog , or prd falling edge t pah 10 ? ns address, data setup to prog or prd t pcs 100 ? ns address, data hold after prog or prd t pch 0?ns pmsel setup to prog or prd t pms 10 ? ns pmsel hold after prog or prd t pmh 10 ? ns prog pulse width t pww 100 ? s prd pulse width t prw 100 ? ns address to valid data out t pad ?75ns prd to valid data out t prd ?20ns data hold after prd t pdh 0?ns data float after prd t pdf ?20ns prog high between two consecutive prog low pulses t pwh1 1? s prd high between two consecutive prd low pulses t pwh2 100 ? ns xtal clock period t clkp 210mhz
c515c data sheet 84 2003-02 figure 35 programming code byte - write cycle timing t paw t pms pah t pas t a8-15 a0-7 d0-7 pcs t pww t pch t t pwh mct03690 h, h pale pmsel1,0 port 2 port 0 prog prd must be high during a programming write cycle. notes:
c515c data sheet 85 2003-02 figure 36 verify code byte - read cycle timing t paw t pms pah t pas t a8-15 a0-7 pad t d0-7 t pdh t pdf prd t pcs t prw t pch t t pwh mct03689 h, h pale pmsel1,0 port 2 port 0 prd notes: prog must be high during a programming read cycle.
c515c data sheet 86 2003-02 figure 37 lock bit access timing h, l h, l d0, d1 d0, d1 t pcs pms t pmh t t pch pww t pms t prd t t pdh pdf t pmh t prw t mct03393 pmsel1,0 port 0 prog prd pale should be low during a lock bit read / write cycle. note:
c515c data sheet 87 2003-02 figure 38 version byte - read timing e. g. fd d0-7 t pcs pms t t pdh pdf t pmh t mct03394 port 2 port 0 prd pmsel1,0 l, h h prw t prd t pch t prog must be high during a programming read cycle. note:
c515c data sheet 88 2003-02 rom/otp verification characteristics for c515c-8r / c515c-8e figure 39 rom verification mode 1 rom verification mode 1 (c515c-8r) parameter symbol limit values unit min. max. address to valid data t avqv ?5 clpns mct02764 inputs: psen = ss v ale, ea = v ih reset = v il2 address port 0 new address data out new data out t avqv data: addresses: p2.0 - p2.7 p1.0 - p1.7 p1.0 - p1.7 = a0 - a7 p2.0 - p2.7 = a8 - a15 p0.0 - p0.7 = d0 - d7
c515c data sheet 89 2003-02 figure 40 rom/otp verification mode 2 rom/otp verification mode 2 parameter symbol limit values unit min. typ. max. ale pulse width t awd ?clp?ns ale period t acy ?6 clp?ns data valid after ale t dva ??2 clpns data stable after ale t dsa 4 clp??ns p3.5 setup to ale low t as ? t cl ?ns oscillator frequency 1 / clp4?6mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
c515c data sheet 90 2003-02 figure 41 ac testing: input, output waveforms figure 42 ac testing: float waveforms figure 43 recommended oscillator ci rcuits for crystal oscillator ac inputs during testing are driven at v dd - 0.5 v for a logic ?1? and 0.45 v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?. 0.45 v v dd 0.2 - 0.1 + 0.9 0.2 dd v test points mct00039 v dd - 0.5 v mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 20 ma mct02765 xtal1 xtal2 xtal2 xtal1 crystal/resonator oscillator mode driving from external source external oscillator signal n.c. 2 - 10 mhz c c c = 20 pf 10 pf (incl. stray capacitance) crystal mode : : resonator mode = depends on selected ceramic resonator c
c515c data sheet 91 2003-02 package outlines 0.65 0.3 12.35 0.1 2 2.45 max 1 80 index marking 17.2 14 0.25 min +0.1 0.88 1) 0.6x45? 1) does not include plastic or metal protrusions of 0.25 max per side a-b 0.2 h d 4x a-b 0.2 d 80x a b d c 0.12 80x d a-b m c 1) 14 17.2 -0.05 h 7?max -0.02 +0.08 0.15 0.08 p-mqfp-80-1 (plastic metric quad flat package) gpm05249 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products. dimensions in mm smd = surface mounted device
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infineon technologies ag - products-~c515c full search home my infineon newsroom contact sitemap products company information investor information careers home > products > microcontrollers > can > can 8-bit > c515c c515c - a multipurpose microcontroller the high peripheral performance and the can feature is ideal for automotive and industrial control applications. due to emc/rfi enhancements and power consumption reduction this design excels especially for car radio applications. c515c 8 bit microcontroller with on-chip full-can module related systems/applications features: l 600 ns instruction cycle time at 10mhz cpu clock without clock prescaler l 15 interrupt vectors with four priority levels selectable l 64 kbyte on-chip rom/otp memory. rom-protection available l 256 byte on-chip internal ram (iram) l 2 kbyte on-chip extended ram (xram) l supports external address range of up to 64 kbyte program and data memory l full can module version 2.0b active with 15 message objects and basic-can feature l synchronous serial interface (ssc) with full spi compatibility l three 16-bit timer/counters l 4 channel capture/compare unit for pwm generation l 8-channel 10-bit a/d converter l full duplex serial interface with asynchronous and synchronous modes and programmable baudrate generator l extended power saving modes l programmable watchdog timer l 80-pin p-mqfp package l temperature ranges: 0c to + 70c / -40c to + 85c / -40c to + 110c typelist (for details see parameterlist) product type description order info to distributor sab c515c-8rm (datasheet) 8-bit cmos microcontroller with mask-programmable rom (10mhz) q67121d1770 saf c515c-8rm (datasheet) 8-bit cmos microcontroller with mask-programmable rom (10mhz) q67127d1783 saf-c515c-lm aa (datasheet) 8-bit cmos microcontroller for external memory (10mhz) q67127c1058 sab c515c-lm (datasheet) 8-bit cmos microcontroller for external memory (10mhz) q67121c1066 saf c515c-8em (datasheet) 8-bit cmos microcontroller with otp memory (10mhz) q67121c2083 additional documentation and information: product brief description date/state size product brief c515c (prodbrief515c.pdf) 06.02.2001 2.15 mb tool brief description date/state size c515c users manual (m515c.pdf) 04.98 800 kb application notes description date/state size changing from the c515a-xm to the c515c-xm (ap0804401_.pdf) 2002-07 | v0.1 18.4 kb changing from the c515-xm to the c515c-xm (ap0804601_.pdf) 2002-07 | v0.1 37.7 kb login username: password: forgotten username/ password? not a user yet? search for products advanced parametric discontinued search help! file://///bnsndv31/prod/prod-image/vip_prod/user/source_issue/si_2004/sep/infn/c515c.htm (1 of 2) [10/27/2004 5:23:06 pm]
infineon technologies ag - products-~c515c c515 - can bit timing - calculation: cp_515cexe 1 (ap082801.exe) 01.98 | rel.0 400 kb c515 - can bit timing - calculation (description) (ap082801.pdf) 01.89 | rel.01 12 kb connecting c166 and c500 microcontrollers to can (81c90,91) (ap290002.pdf) 06.97 | rel.01 833 kb the can controller in the c515c (apnote) (ap082001.pdf) 12.96 | rel.01 445 kb the can controller in the c515c (prog-file) (ap082001.exe) 05.97 | rel.01 19 kb power supply concept for the c515c (ap082501.pdf) 05.97 rel.01 57 kb errata sheet description date/state size c515c-8em (c515c-8e_bb_14.pdf) 12.06.2001 26.6 kb c515c_8em_bc (c515c-8e_bc_11.pdf) 2003-12 | v1.1 87.4 kb c515c-lm/4rm/8rm aa step (c515c-l-8r_aa_15.pdf) 2003-12 | v1.5 99.6 kb c515c-l/4r/8r (c515-l-8r_aa14.pdf) 12.09.2001 29.9 kb ? 1999 - 2004 infineon technologies ag - usage of this web site is subject to the usage terms. file://///bnsndv31/prod/prod-image/vip_prod/user/source_issue/si_2004/sep/infn/c515c.htm (2 of 2) [10/27/2004 5:23:06 pm]

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